This invention relates to semiconductor devices, and more particularly to the assembly and packaging of such devices.
The packaging of the semiconductor device serves to protect the device from the environment in which it is to be used, as well as to provide electrical contacts for connection of the device within its environment.
Packaging for semiconductor devices are known in a variety of configurations, including those which are hermetic (gas-tight). Design criteria therefore leads to a consideration of the need to dissipate heat, the current and voltage capacity, and the topography of the semiconductor device.
For example, U.S. Patent No. 5,139,972 relates to low cost fabrication of hermetic thin packagings of high density power semiconductors, and to methods for fabrication by batch assembly. The method includes providing silicon chip arrays with thermocompressively bonded foil contacts, ceramic lid arrays which contain upper surface and lower margin direct-bonded copper coverings and through-the-lid high current conductors, such as spherical conductors, coining cup arrays, such as from copper, die mounting a semiconductor chip in each cup, registering the lid and cup arrays, and solder reflowing to hermetically seal the hermetic thin packagings.
U.S. Pat. No. 5,248,901 relates to semiconductor devices and methods for their assembly. This patent discloses a semiconductor device package including a cup-like base having an encircling side wall having at its upper end a laterally outwardly extending metal flange. A lid for the package includes a plate-like member having at the lower peripheral edge thereof an outwardly laterally extending metal flange which overlaps and is bonded to the base flange. The lid can have apertures therethrough which are sealed by metal foils bonded to the lower surface of the lid. The metal foils overlie and are bonded to electrodes on the upper surface of the chip within the package. The lid can also have a hollow tubing extending into each aperture in hermetic fit with the aperture wall. The chip within the semiconductor device package includes terminal leads extending into the tubings and hermetically bonded to the tubing inner walls.
U.S. Pat. No. 5,521,436 relates to a semiconductor device with a foil-sealed lid. The semiconductor device has a semiconductor substrate that includes a layer of metal on its upper surface along the substrate outer edge and spaced from the electrodes on the substrate upper surface. The ceramic plate forming a lid portion includes a copper foil on its lower surface along the outer edge thereof which overlaps and is bonded to the substrate metal layer. The ceramic plate has apertures that are sealed by copper foil on the package inside, with the foils being bonded to respective substrate electrodes.
U.S. Pat. No. 5,366,932 relates to a semiconductor chip packaging method and semiconductor chip having interdigitated gate runners with gate bonding pads. The gate runners overlie and contact selected gate electrodes on the chip surface, as well as have an integral widened area to enable bonding to a package-carried gate electrode contact foil. Also, the gate runners have portions that underlie a package-carried power electrode contact foil and are separated therefrom by a nonbondable, insulating layer. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as an active chip area. Also, package lid-to-chip alignment tolerances may be relaxed as they are not dictated by alignment of the lid carried gate contact foil with the gate electrode on the chip.
Semiconductor devices for which the present invention may find application include various solid state power devices, such as, for example, MOSFETs, MOS gated semiconductor devices, MOS controlled thyristors (MCTs), insulated gate bipolar transistors(IGBTs), conductivity modulated field effect transistors (COMFETS), and other solid state power devices, including those having a cellular topography.
A goal in semiconductor device packaging is to provide smaller and lighter packaging for semiconductor devices at a reasonable cost and with reduced complexity.
A further goal in semiconductor device packaging is to achieve a hermetically sealed semiconductor device package of reasonable cost, durability, and simplicity.
Accordingly, it is an object of the present invention to provide a novel hermetic thin pack semiconductor device of reasonable cost.
It is another object of the present invention to provide a novel hermetic thin pack semiconductor device that is durable and simple in construction.
It is yet another object of the present invention to provide a novel hermetic thin pack semiconductor device that promotes ease of manufacture.
It is still another object of the present invention to provide a novel thin pack semiconductor device for use in high density power packages.
It is a further object of the present invention to provide a novel thin pack semiconductor device for solid state power devices having a cellular topography.
The present invention promotes the above objectives by providing a thin pack semiconductor device having a semiconductor substrate with at least one electrode of an electrically conductive material on at least a portion of the upper surface of the semiconductor substrate, and having a lid of a ceramic material, the lid having at least one opening. A first electrically conductive material is located on the interior surface of the at least one opening, a second electrically conductive material is located on at least a portion of the upper surface of the lid, and a third electrically conductive material is located on at least a portion of the lower surface of the lid. A solder material is positioned between the at least one electrode located on the upper surface of the semiconductor substrate and the third electrically conductive material located on the lower surface of the lid and positioned on a corresponding portion of the at least one electrode opposite a corresponding opening in the lid which may serve to hermetically seal the semiconductor device.
Preferably the first, second and third electrically conductive materials include copper.
It is also desirable that the solder material fills the at least one opening in the lid of the hermetic thin pack semiconductor device.
In some embodiments, it is further desirable that the solder material be positioned around an outer peripheral portion of the thin pack semiconductor device between the lower surface of the lid and the upper surface of the semiconductor substrate to complete a hermetic seal of the device. However, peripheral solder is not always needed or desired. For example, the periphery could be closed using a non-hermetic material or even could be left open. In the latter situation, an open periphery device could be placed, perhaps with other similar devices, within another package to provide any desired resistance to contamination and external environmental factors.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.